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TMS370 Datasheet(PDF) 68 Page - Texas Instruments |
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TMS370 Datasheet(HTML) 68 Page - Texas Instruments |
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68 / 73 page  TMS370Cx6x 8-BIT MICROCONTROLLER SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997 68 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SPI-slave mode external timing characteristics and requirements (see Note 14 and Figure 32) NO. MIN MAX UNIT 45 tc(SPC)S Cycle time, SPICLK 8tc ns 46 tw(SPCL)S Pulse duration, SPICLK low 4tc – 45 0.5tc(SPC)S+45 ns 47 tw(SPCH)S Pulse duration, SPICLK high 4tc – 45 0.5tc(SPC)S+45 ns 48 td(SPCL-SOMIV)S Delay time, SPISOMI valid after SPICLK low (polarity = 1) 3.25tc + 130 ns 49 tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (polarity =1) tw(SPCH)S ns 50 tsu(SIMO-SPCH)S Setup time, SPISIMO to SPICLK high (polarity = 1) 0 ns 51 tv(SPCH-SIMO)S Valid time, SPISIMO data after SPICLK high (polarity = 1) 3tc + 100 ns NOTE 14: tc = system-clock cycle time = 1 / SYSCLK Data Valid Data Valid SPISOMI SPISIMO SPICLK 51 50 49 48 45 47 46 NOTE A: The diagram shows polarity = 1. SPICLK is inverted when polarity = 0. Figure 32. SPI-Slave External Timing |
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