TMS370 datasheet(10/73 Pages) TI

10 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

CPU (continued)

The ’x6x CPU architecture provides the following components:

D CPU registers:

–

A stack pointer that points to the last entry in the memory stack

–

A status register that monitors the operation of the instructions and contains the global-interrupt-enable

bits

–

A program counter (PC) that points to the memory location of the next instruction to be executed

D A memory map that includes :

–

1K- or 3.5K-byte general-purpose RAM that can be used for data-memory storage, program

instructions, general-purpose register, or the stack (can be located only in the first 256 bytes)

–

A peripheral file that provides access to all internal peripheral modules, system-wide control functions,

and EEPROM/EPROM programming control

–

256-byte EEPROM module that provides in-circuit programmability and data retention in power-off

conditions

–

24K-, 32K-, or 48K-byte ROM or 32K-, or 48K-byte EPROM program memory

stack pointer (SP)

The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. The stack is used

typically to store the return address on subroutine calls as well as the status-register contents during interrupt

sequences.

The SP points to the last entry or to the top of the stack. The SP increments automatically before data is pushed

onto the stack and decrements after data is popped from the stack. The stack can be located only in the first

256 bytes of the on-chip RAM memory.

status register (ST)

The ST monitors the operation of the instructions and contains the global-interrupt-enable bits. The ST includes

four status bits (condition flags) and two interrupt-enable bits:

D The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,

the conditional-jump instructions) use these status bits to determine program flow.

D The two interrupt-enable bits control the two interrupt levels.

The ST register, status bit notation, and status bit definitions are shown in Table 4.

Table 4. Status Registers

IE2

IE1

Reserved

RW-0

R = read, W = write, 0 = value after reset

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