TMS370 datasheet(9/73 Pages) TI

9 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

CPU

The CPU used on TMS370Cx6x devices is the high-performance 8-bit TMS370 CPU module. The ’x6x

implements an efficient register-to-register architecture that eliminates the conventional accumulator

bottleneck. The complete ’x6x instruction set is summarized in Table 22. Figure 1 illustrates the CPU registers

and memory blocks.

0000h

0400h

1000h

10C0h

1100h

Interrupts and Reset Vectors;

Trap Vectors

FFFFh

RAM (Includes 256-Byte Registers File)

Program Counter (PC)

Legend:

Z=Zero

IE1=Level1 interrupts Enable

C=Carry

V=Overflow

N=Negative

IE2=Level2 interrupts Enable

IE1

IE2

Status Register (ST)

Stack Pointer (SP)

R0(A)

R1(B)

R127

0000h

0001h

0002h

007Fh

R255

0003h

00FFh

Reserved†

24K-Byte ROM (2000h – 7FFFh)

1F00h

0100h

0E00h

32K-Byte ROM / EPROM (2000h – 9FFFh)

48K-Byte ROM / EPROM (2000h – DFFFh)

Memory Expansion

2000h

7FBEh

A000h

E000h

1K-Byte RAM (0000h – 03FFh)

3.5K-Byte RAM (0000h – 0DFFh)

Peripheral File

Peripheral Expansion

Reserved

256-Byte Data EEPROM

00FFh

03FFh

0FFFh

10BFh

10FFh

1EFFh

0DFFh

1FFFh

7FBDh

8000h

7FFFh

9FFFh

DFFFh

† Reserved means the address space is reserved for future expansion.

Figure 1. Programmer’s Model

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