TMS370 datasheet(17/73 Pages) TI

17 / 73 page

TMS370Cx6x

8-BIT MICROCONTROLLER

SPNS033C – SEPTEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

interrupts

The TMS370 family software programmable interrupt structure permits flexible on-chip and external interrupt

configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure

incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt

level 2. The two priority levels can be independently masked by the global-interrupt mask bits (IE1 and IE2) of

the status register.

Each system interrupt is independently configured to either the high- or low-priority chain by the application

program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of

the system interrupt. However, since each system interrupt is selectively configured on either the high-or-low

priority interrupt chain, the application program can elevate any system interrupt to the highest priority.

Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority

chains is performed within the peripheral modules to support interrupt expansion for future modules. Pending

interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and

priority conditions.

The TMS370Cx6x has ten hardware system interrupts (plus RESET) as shown in Table 11. Each system

interrupt has a dedicated vector located in program memory through which control is passed to the interrupt

service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXINT has two interrupt

sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in the

associated PF. Each interrupt source FLAG bit is individually readable for software polling or to determine which

interrupt source generated the associated system interrupt. Interrupt control block diagram is illustrated in

Figure 4.

TMS370 Datasheet(PDF) 17 Page - Texas Instruments