DS1876 datasheet(18/69 Pages) MAXIM

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18 _____________________________________________________________________________________

SFP Controller with Dual LDD Interface

Digital I/O Pins

Six digital input pins and five digital output pins are pro-

vided for monitoring and control.

IN1, RSEL, OUT1, RSELOUT

Digital input pins IN1 and RSEL primarily serve to meet

the rate-select requirements of SFP and SFP+. They

can also serve as general-purpose inputs. OUT1 and

RSELOUT are driven by a combination of the IN1, RSEL,

and logic dictated by control registers in the EEPROM

(see Figure 10). The levels of IN1 and RSEL can be

read from the STATUS register (Lower Memory, Register

6Eh). The open-drain output OUT1 can be controlled

and/or inverted using the CNFGB register (Table 02h,

software controlled and/or inverted through the STATUS

External pullup resistors must be provided on OUT1 and

RSELOUT to realize high logic levels.

TXF1, TXF2, TXFOUT, TXD1, TXD2,

TXDOUT1, TXDOUT2

TXDOUT1 and TXDOUT2 are generated from a com-

bination of TXF1, TXF2, TXD1, TXD2, and the internal

signals FETG1 and FETG2 (Table 02h, Register 8Ah). A

software control identical to TXD1 and TXD2 is also avail-

able (TXDC1 and TXDC2, Lower Memory, Register 6Eh).

A TXD1 or TXD2 pulse is internally extended (TXDEXT)

by time tINITR1 to inhibit the latching of low alarms and

warnings related to the APC loop to allow for the loop to

stabilize. The nonlatching alarms and warnings are TXP

LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2

LO. In addition, TXP LO is disabled from creating FETG.

See the Transmit Fault (TXFOUT) Output section for a

detailed explanation of TXFOUT. As shown in Figure 9,

the same signals and faults can also be used to gener-

ate the internal signal FETG. FETG is used to send a fast

“turn-off” command to the laser driver. The intended use

is a direct connection to the laser driver’s TXD1, TXD2

input if this is desired. When VCC < POA, TXDOUT1 and

TXDOUT2 are high impedance.

Figure 9. Logic Diagram 1

Figure 10. Logic Diagram 2

OUT

TXDS_

TXFS_

RPU

SET BIAS_ DAC AND

MOD_ DAC TO HIGH

IMPEDANCE

TXD_

TXFINT

INVTXF_

TXFOUTS1

TXFOUTS2

TXF_

TXP_ HI FLAG

TXP HI ENABLE

HBAL_ FLAG

HBAL ENABLE

QTHEXT_

TXP_ LO FLAG

TXP LO ENABLE

TXDEXT (tINITR1)

TXDC_

VCC

TXD_

TXDOUT_

TXFOUTS_

TXDIO_

TXDFG_

FETG_

TXDFLT_

FAULT RESET TIMER

(130ms)

OUT

POWER-ON

RESET

TXFOUT

NOTE:

_ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2.

REFERS TO A PIN.

INVOUT1

IN1C

IN1

IN1S

OUT1

INVRSOUT

RSELOUT

RSELC

RSEL

RSELS

= PINS

DS1876 Datasheet(PDF) 18 Page - Maxim Integrated Products

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