DS1876 datasheet(20/69 Pages) MAXIM

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SFP Controller with Dual LDD Interface

of SCL during a bit read. The device shifts out each

bit of data on SDA at the falling edge of the previous

SCL pulse and the data bit is valid at the rising edge

of the current SCL pulse. Remember that the master

generates all SCL clock pulses, including when it is

reading bits from the slave.

Acknowledgement (ACK and NACK): An acknowl-

edgement (ACK) or not-acknowledge (NACK) is

always the 9th bit transmitted during a byte transfer.

The device receiving data (the master during a read

or the slave during a write operation) performs an ACK

by transmitting a zero during the 9th bit. A device per-

forms a NACK by transmitting a one during the 9th bit.

Timing (Figure 12) for the ACK and NACK is identical

to all other bit writes. An ACK is the acknowledgment

that the device is properly receiving data. A NACK is

used to terminate a read sequence or as an indication

that the device is not receiving data.

Byte Write: A byte write consists of 8 bits of informa-

tion transferred from the master to the slave (most

significant bit first) plus a 1-bit acknowledgement from

the slave to the master. The 8 bits transmitted by the

master are done according to the bit write definition

and the acknowledgement is read using the bit read

definition.

Byte Read: A byte read is an 8-bit information transfer

from the slave to the master plus a 1-bit ACK or NACK

from the master to the slave. The 8 bits of information

that are transferred (most significant bit first) from the

slave to the master are read by the master using the

bit read definition, and the master transmits an ACK

using the bit write definition to receive additional data

bytes. The master must NACK the last byte read to

terminate communication so the slave returns control

of SDA to the master.

Slave Address Byte: Each slave on the I2C bus

responds to a slave address byte sent immediately

following a START condition. The slave address byte

contains the slave address in the most significant 7bits

and the R/W bit in the least significant bit.

The DS1876 responds to three slave addresses. The

auxiliary memory always responds to a fixed I2C slave

address, A0h. (If the main device’s slave address

is programmed to be A0h, access to the auxiliary

memory is disabled.) The Lower Memory and Tables

00h–06h respond to I2C slave addresses whose lower

3 bits are configurable (A0h–AEh, B0h

-BEh) using the

DEVICE ADDRESS byte (Table 02h, Register 8Bh). The

user also must set the ASEL bit (Table 02h, Register

88h) for this address to be active. By writing the cor-

rect slave address with R/W = 0, the master indicates

it writes data to the slave. If R/W = 1, the master reads

data from the slave. If an incorrect slave address is

written, the DS1876 assumes the master is communi-

cating with another I2C device and ignores the com-

munications until the next START condition is sent.

Memory Address: During an I2C write operation

to the DS1876, the master must transmit a memory

address to identify the memory location where the

slave is to store the data. The memory address is

Figure 12. I2C Timing

SCL

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

SDA

STOP

START

REPEATED

START

tBUF

tHD:STA

tHD:DAT

tSU:DAT

tSU:STO

tHD:STA

tSP

tSU:STA

tHIGH

tLOW

DS1876 Datasheet(PDF) 20 Page - Maxim Integrated Products

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