DS1876 datasheet(22/69 Pages) MAXIM

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SFP Controller with Dual LDD Interface

EEPROM Write Cycles: When EEPROM writes occur,

the DS1876 writes the whole EEPROM memory page,

even if only a single byte on the page was modified.

Writes that do not modify all 8 bytes on the page are

allowed and do not corrupt the remaining bytes of

memory on the same page. Because the whole page

is written, bytes on the page that were not modi-

fied during the transaction are still subject to a write

cycle. This can result in a whole page being worn

out over time by writing a single byte repeatedly.

Writing a page 1 byte at a time wears the EEPROM

out 8x faster than writing the entire page at once. The

DS1876’s EEPROM write cycles are specified in the

Nonvolatile Memory Characteristics table. The speci-

fication shown is at the worst-case temperature. It can

handle approximately 10x that many writes at room

temperature. Writing to SRAM-shadowed EEPROM

memory with SEEB = 1 does not count as a EEPROM

write cycle when evaluating the EEPROM’s estimated

lifetime.

Reading a Single Byte from a Slave: Unlike the

write operation that uses the memory address byte

to define where the data is to be written, the read

operation occurs at the present value of the memory

address counter. To read a single byte from the slave,

the master generates a START condition, writes the

slave address byte with R/W = 1, reads the data byte

with a NACK to indicate the end of the transfer, and

generates a STOP condition.

Manipulating the Address Counter for Reads: A

dummy write cycle can be used to force the address

pointer to a particular value. To do this, the mas-

ter generates a START condition, writes the slave

address byte (R/W = 0), writes the memory address

where it desires to read, generates a repeated START

condition, writes the slave address byte (R/W = 1),

reads data with ACK or NACK as applicable, and

generates a STOP condition.

Memory Organization

The DS1876 features nine separate memory tables

that are internally organized into 8-byte rows. The main

device located at A2h is used for overall device con-

figuration and transmitter 1 control, calibration, alarms,

warnings, and monitoring.

Lower Memory, A2h is addressed from 00h–7Fh and

contains alarm and warning thresholds, flags, masks,

several control registers, password entry area (PWE),

and the table-select byte.

Table 01h, A2h primarily contains user EEPROM (with

PW1 level access) as well as alarm and warning enable

bytes.

Table 02h, A2h/B2h is a multifunction space that con-

tains configuration registers, scaling and offset values,

passwords, and interrupt registers as well as other mis-

cellaneous control bytes. All functions and status can be

written and read from either A2h or B2h addresses.

Table 04h, A2h contains a temperature-indexed LUT for

control of the MOD1 voltage. The MOD1 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the MOD1 offsets.

Table 05h, A2h is empty by default. It can be config-

ured to contain the alarm and warning enable bytes

from Table 01h, Registers F8h–FFh with the MASK bit

enabled (Table 02h, Register 88h). In this case Table

01h is empty.

Table 06h, A2h contains a temperature-indexed LUT for

control of the APC1 voltage. The APC1 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the APC1 offsets.

The main device located at B2h is used for transmitter 2

control, calibration, alarms, warnings, and monitoring.

Lower Memory, B2h is addressed from 00h–7Fh and

contains alarm and warning thresholds, flags, masks,

several control registers, PWE, and the table-select byte.

Table 01h, B2h contains alarm and warning enable

bytes.

Table 04h, B2h contains a temperature-indexed LUT for

control of the MOD2 voltage. The MOD2 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the MOD2 offsets.

Table 05h, B2h is empty by default. It can be config-

ured to contain the alarm and warning enable bytes

from Table 01h, Registers F8h–FFh with the MASK bit

enabled (Table 02h, Register 88h). In this case Table

01h is empty.

Table 06h, B2h contains a temperature-indexed LUT for

control of the APC2 voltage. The APC2 LUT can be pro-

grammed in 2NC increments over the -40NC to +102NC

range. This also contains a temperature-indexed LUT for

the APC2 offsets.

DS1876 Datasheet(PDF) 22 Page - Maxim Integrated Products

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