AM3892 datasheet(242/299 Pages) TI

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LOAD

Reconstruction

Filter

IOUTx

75 W

SD:

9.5 MHZ

ED:

18 MHZ

HD:

36 MHz

1080p: 72 MHz

Amplifier

SD: 5.6 V/V

HD: 4.5 V/V

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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8.10.3 Video DAC Guidelines and Electrical Data/Timing

The device's analog video DAC outputs are designed to drive a 37.5-

Ω load. Figure 8-71 describes a

typical circuit that permits connecting the analog video output from the device to standard 75-

Ω impedance

video systems. The device requires the use of a buffer to drive the actual video outputs, so one solution is

to use a video amplifier with integrated buffer and internal filter, such as the Texas Instruments THS7360,

which provides a complete solution for the typical output circuit shown in Figure 8-71.

Figure 8-71. Typical Output Circuits for Analog Video from DACs

During board design, the onboard traces and parasitics must be matched for the channel. The video DAC

output pin (IOUTx) is a very high-frequency analog signal and must be routed with extreme care. As a

result, the path of this signal must be as short as possible, and as isolated as possible from other

interfering signals. The load resistor and amplifier/buffer should be placed close together and as close as

possible to the device pins. Other layout guidelines include:

•

Take special care to bypass the DAC power supply pin with a capacitor.

•

Place the 75-

Ω resistor as close as possible (<0.5") to the amplifier/buffer (THS7360) output pin.

•

To maintain a high quality video signal, 75-

Ω (±10%) characteristic impedance traces should be used

after the 75-

Ω series resistor.

•

Minimize input trace lengths to the device to reduce parasitic capacitance.

•

Include solid ground return paths.

•

Match trace lengths as close as possible within a video format group (i.e., Y, Pb, and Pr for component

output, and Y and C for s-video output should match each other).

For additional video DAC design guidelines, see the HDVPSS chapter in the AM38x Sitara ARM

Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7).

Table 8-73. DAC Specifications

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

HD DACs

Bits

SD DACs

Bits

DC Accuracy - HD DACs

Integral Non-Linearity (INL), best fit

HD DACs

1.5

LSB

SD DACs

1.0

LSB

Differential Non-Linearity (DNL)

HD DACs

1.0

LSB

SD DACs

0.5

LSB

Analog Output

Output Resistor (RLOAD)

HD and SD DACs

-1%

37.5

+1%

Full-Scale Output Current (IFS)

HD and SD DACs

13.3

RLOAD

Output Compliance Range

HD and SD DACs

Vref

IFS = 13.3 mA,

RLOAD = 37.5 Ω

Zero Scale Offset Error (ZSET)

HD and SD DACs

0.5

LSB

Gain Error

HD and SD DACs

-10

242

Peripheral Information and Timings

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