AM3892 datasheet(240/299 Pages) TI

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VIN[x]A_CLK/

VIN[x]B_CLK/

VOUT[x]_CLK

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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Table 8-72. Switching Characteristics Over Recommended Operating Conditions for HDVPSS Output

(see Figure 8-68 and Figure 8-70)

NO.

PARAMETER

MIN

MAX

UNIT

tc(CLK)

Cycle time, VOUT[x]_CLK

6.06(1)

tw(CLKH)

Pulse duration, VOUT[x]_CLK high (45% of tc)

2.73

tw(CLKL)

Pulse duration, VOUT[x]_CLK low (45% of tc)

2.73

tt(CLK)

Transition time, VOUT[x]_CLK (10%-90%)

2.64

td(CLK-AVID)

td(CLK-FLD)

Delay time, VOUT[x]_CLK to control valid

1.64(2)

4.18(3)

td(CLK-VSYNC)

td(CLK-HSYNC)

td(CLK-RCR)

td(CLK-GYYC)

Delay time, VOUT[0]_CLK to data valid

td(CLK-BCBC)

1.64(2)

4.18(3)

td(CLK-YYC)

Delay time, VOUT[1]_CLK to data valid

td(CLK-C)

(1)

For maximum frequency of 165 MHz.

(2)

Min Delay Time = Tc * 0.27, where Tc is the clock cycle time. Note: Must match board trace length delay for clock and data to within

0.34 ns.

(3)

Max Delay Time = Tc * 0.69, where Tc is the clock cycle time. Note:Must match board trace length delay for clock and data to within

0.34 ns.

Figure 8-68. HDVPSS Clock Timing

240

Peripheral Information and Timings

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