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AM3892 Datasheet(PDF) 244 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 244 Page - Texas Instruments |
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244 / 299 page  AM3894 AM3892 SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 www.ti.com 8.11 Inter-Integrated Circuit (I2C) The device includes two inter-integrated circuit (I2C) modules which provide an interface to other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through the I2C module. The I2C port does not support CBUS compatible devices. The I2C port supports the following features: • Compatible with Philips I2C Specification Revision 2.1 (January 2000) • Standard and fast modes from 10 - 400 Kbps (no fail-safe I/O buffers) • Noise filter to remove noise 50 ns or less • Seven- and ten-bit device addressing modes • Multimaster transmitter/slave receiver mode • Multimaster receiver/slave transmitter mode • Combined master transmit/receive and receive/transmit modes • Two DMA channels, one interrupt line • Built-in FIFO (32 byte) for buffered read or write. For more detailed information on the I2C peripheral, see the I2C chapter in the AM38x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (literature number SPRUGX7). 8.11.1 I2C Peripheral Register Descriptions Table 8-74. I2C Registers I2C0 HEX ADDRESS I2C1 HEX ADDRESS ACRONYM REGISTER NAME 0x4802 8000 0x4802 A000 I2C_REVNB_LO Module Revision (LOW BYTES) 0x4802 8004 0x4802 A004 I2C_REVNB_HI Module Revision (HIGH BYTES) 0x4802 8010 0x4802 A010 I2C_SYSC System configuration 0x4802 8020 0x4802 A020 I2C_EOI I2C End of Interrupt 0x4802 8024 0x4802 A024 I2C_IRQSTATUS_RAW I2C Status Raw 0x4802 8028 0x4802 A028 I2C_IRQSTATUS I2C Status 0x4802 802C 0x4802 A02C I2C_IRQENABLE_SET I2C Interrupt Enable Set 0x4802 8030 0x4802 A030 I2C_IRQENABLE_CLR I2C Interrupt Enable Clear 0x4802 8034 0x4802 A034 I2C_WE I2C Wakeup Enable 0x4802 8038 0x4802 A038 I2C_DMARXENABLE_SET Receive DMA Enable Set 0x4802 803C 0x4802 A03C I2C_DMATXENABLE_SET Transmit DMA Enable Set 0x4802 8040 0x4802 A040 I2C_DMARXENABLE_CLR Receive DMA Enable Clear 0x4802 8044 0x4802 A044 I2C_DMATXENABLE_CLR Transmit DMA Enable Clear 0x4802 8048 0x4802 A048 I2C_DMARXWAKE_EN Receive DMA Wakeup 0x4802 804C 0x4802 A04C I2C_DMATXWAKE_EN Transmit DMA Wakeup 0x4802 8090 0x4802 A090 I2C_SYSS System Status 0x4802 8094 0x4802 A094 I2C_BUF Buffer Configuration 0x4802 8098 0x4802 A098 I2C_CNT Data Counter 0x4802 809C 0x4802 A09C I2C_DATA Data Access 0x4802 80A4 0x4802 A0A4 I2C_CON I2C Configuration 0x4802 80A8 0x4802 A0A8 I2C_OA I2C Own Address 0x4802 80AC 0x4802 A0AC I2C_SA I2C Slave Address 0x4802 80B0 0x4802 A0B0 I2C_PSC I2C Clock Prescaler 0x4802 80B4 0x4802 A0B4 I2C_SCLL I2C SCL Low Time 0x4802 80B8 0x4802 A0B8 I2C_SCLH I2C SCL High Time 0x4802 80BC 0x4802 A0BC I2C_SYSTEST System Test 244 Peripheral Information and Timings Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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