AM3892 datasheet(239/299 Pages) TI

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AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

8.10.2 HDVPSS Electrical Data/Timing

Table 8-71. Timing Requirements for HDVPSS Input

(see Figure 8-68 and Figure 8-69)

NO.

MIN

MAX

UNIT

VIN[x]A_CLK

tc(CLK)

Cycle time, VIN[x]A_CLK

6.06(1)

tw(CLKH)

Pulse duration, VIN[x]A_CLK high (45% of tc)

2.73

tw(CLKH)

Pulse duration, VIN[x]A_CLK low (45% of tc)

2.73

tt(CLK)

Transition time, VIN[x]A_CLK (10%-90%)

2.64

tsu(DE-CLK)

tsu(VSYNC-CLK)

Input setup time, control valid to VIN[x]A_CLK high

3.11

tsu(FLD-CLK)

tsu(HSYNC-CLK)

tsu(D-CLK)

Input setup time, data valid to VIN[x]A_CLK high

3.11

th(CLK-DE)

th(CLK-VSYNC)

Input hold time, control valid from VIN[x]A_CLK high

-0.05

th(CLK-FLD)

th(CLK-HSYNC)

th(CLK-D)

Input hold time, data valid from VIN[x]A_CLK high

-0.05

VIN[x]B_CLK

tc(CLK)

Cycle time, VIN[x]B_CLK

6.06(1)

tw(CLKH)

Pulse duration, VIN[x]B_CLK high (45% of tc)

2.73

tw(CLKH)

Pulse duration, VIN[x]B_CLK low (45% of tc)

2.73

tt(CLK)

Transition time, VIN[x]B_CLK (10%-90%)

2.64

tsu(DE-CLK)

tsu(VSYNC-CLK)

Input setup time, control valid to VIN[x]B_CLK high

3.11

tsu(FLD-CLK)

tsu(HSYNC-CLK)

tsu(D-CLK)

Input setup time, data valid to VIN[x]B_CLK high

3.11

th(CLK-DE)

th(CLK-VSYNC)

Input hold time, control valid from VIN[x]B_CLK high

-0.05

th(CLK-FLD)

th(CLK-HSYNC)

th(CLK-D)

Input hold time, data valid from VIN[x]B_CLK high

-0.05

(1)

For maximum frequency of 165 MHz.

Peripheral Information and Timings

239

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