900844 datasheet(7/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

INTERNAL BLOCK DIAGRAM

ADIN18

SGNL

4.8 V

AJ17

ADC generic input 9

ADIN19

SGNL

4.8 V

AH16

ADC generic input 10

ADIN20

SGNL

4.8 V

W15

ADC generic input 11

ADIN21

SGNL

4.8 V

AC15

ADC generic input 12

TSREF

LOPWR

3.6 V

W17

Reference for touchscreen interface

GNDADC

LOPWRGND

V16

Ground reference for ADC

Oscillator and Real Time Clock - RTC

XTAL1

SGNL

2.5 V

AG19

32.768 kHz oscillator crystal connection 1

XTAL2

SGNL

2.5 V

AF18

32.768 kHz oscillator crystal connection 2

CLK32K

SGNL

3.6 V

AH22

32 kHz clock output

GNDRTC

GND

AJ21

Ground for the RTC block

Platform Architecture Sideband Signals

PMICINT

SGNL

2.5 V

B16

PMIC Interrupt. Asserted by PMIC to wake platform

controller hub and begin communications. Level-sensitive,

read to clear.

VRCOMP

SGNL

2.5 V

H16

Voltage regulator complete. Asserted high by the PMIC

when a SPI voltage regulation request has been decoded.

The signal is de-asserted on completion of the request (i.e.

the rail is in regulation).

RESETB

SGNL

2.5 V

C15

Active low hard reset for platform controller hub. When

asserted, the platform controller hub should return to its

initial default state.

PWRGD

SGNL

2.5 V

M16

POWER GOOD: The 900844 asserts this signal to indicate

that all power rails to the platform controller hub are good.

Assertion of PWRGD also means that VCCA_OSC has

been valid for at least 30 microseconds. The Platform

Controller Hub will remain “off” until this signal is asserted.

EXITSTBY

SGNL

2.5 V

J17

EXIT Standby. When asserted, the 900844 exits the AOAC

standby settings for regulating the platform supplies. When

asserted, the 900844 switches VRs on which are defined in

registers 0x09 through 0x0D. This is a low latency VR

context switch.

THERMTRIPB

SGNL

1.5 V

G17

Thermal trip. Asserted by the CPU to indicate a catastrophic

thermal event.

VIDEN0

SGNL

1.5 V

Driven by the CPU to indicate which VR the VID bus is

addressed to (VCC or VNN). Debounced inside the 900844

for 150 ns. The CPU will hold the value for at least 300 ns.

VIDEN1

SGNL

1.5 V

VID0

SGNL

1.5 V

Driven by the CPU to indicate the output voltage setting for

the VCC and VNN rails. Debounced inside the 900844 for

150 ns. The CPU will hold the value for at least 300 ns.

VID1

SGNL

1.5 V

VID2

SGNL

1.5 V

VID3

SGNL

1.5 V

VID4

SGNL

1.5 V

VID5

SGNL

1.5 V

VID6

SGNL

1.5 V

GNDCTRL

GND

AB14

Logic Control Ground

Table 1. 900844 Pin Description

Node Name

Type

I/O

Rating

# of

Balls

BGA Location

Pin Description

900844 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc

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