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OR3C80 Datasheet(PDF) 116 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 116 Page - Agere Systems |
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116 / 210 page  116 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 49. Microprocessor Interface (MP I) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. 1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go inactive before the end of the read/write cycle. 2. 0.5 MPI_CLK. 3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized. 4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV. 5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle. 6. USTART_DEL is based on the falling clock edge. 7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle. 8. The user must assert interrupt request low until a service routine is executed. 9. This should be at least one MPI_CLK cycle. 10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing. Notes: Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA. PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK). Parameter Symbol Speed Unit –4 –5 –6 –7 Min Max Min Max Min Max Min Max User Logic Delay(5) User Logic Delay —— —— —— —— ns User Start Delay (MPI_CLK falling to USTART)(6) USTART_DEL — 3.6 — 3.4 — 3.3 — 2.8 ns User Start Clear Delay (MPI_CLK to USTART) USTARTCLR_DEL — 7.5 — 7.3 — 7.1 — 6.0 ns User End Delay (USTART low to UEND low)(7) UEND_DEL — — — — — — — — ns Synchronous User Timing: User End Setup (UEND to MPI_CLK) UEND_SET 0.00 — 0.00 — 0.00 — 0.00 — ns User End Hold (UEND to MPI_CLK) UEND_HLD 1.0 — 0.95 — 0.88 — 0.75 — ns Data Setup for Read (D[7:0] to MPI_CLK)(9) RDS_SET —— —— —— —— ns Data Hold for Read (D[7:0] from MPI_CLK)(9) RDS_HLD —— —— —— —— ns Asynchronous User Timing: User End to Read Data Delay (UEND to D[7:0])(10) RDA_DEL —— —— —— —— ns Data Hold from User Start (low)(9) RDA_HLD —— —— —— —— ns Interrupt Request Pulse Width(8) TUIRQ_PW —— —— —— —— ns |
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