OR3C80 datasheet(112/210 Pages) AGERE

112 / 210 page

112

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

PIO Timing

Table 48. Programmable I/O (PIO) Timing Characteristics

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Parameter

Symbol

Speed

Unit

-4

-5

-6

-7

Min

Max

Min

Max

Min

Max

Min

Max

Input Delays (TJ = 85 °C, VDD = min)

Input Rise Time

IN_RIS

—

500

—

500

—

500

—

500

Input Fall Time

IN_FAL

—

500

—

500

—

500

—

500

PIO Direct Delays:

Pad to In (pad to CLK IN)

Pad to In (pad to IN1, IN2)

Pad to In Delayed (pad to IN1, IN2)

CKIN_DEL

IN_DEL

IND_DEL

—

1.41

2.16

9.05

—

1.26

1.87

7.83

—

0.64

1.28

6.64

—

0.41

0.90

7.27

PIO Transparent Latch Delays:

Pad to In (pad to IN1, IN2)

Pad to In Delayed (pad to IN1, IN2)

LATCH_DEL

LATCHD_DEL

—

4.11

10.58

—

3.25

9.05

—

2.52

7.67

—

1.82

7.65

Input Latch/FF Setup Timing:

Pad to ExpressCLK (fast-capture latch/FF)

Pad Delayed to ExpressCLK

(fast-capture latch/FF)

Pad to Clock (input latch/FF)

Pad Delayed to Clock (input latch/FF)

Clock Enable to Clock (CE to CLK)

Local Set/Reset (sync) to Clock (LSR to CLK)

INREGE_SET

INREGED_SET

INREG_SET

INREGD_SET

INCE_SET

INLSR_SET

5.93

12.86

1.62

8.57

2.03

1.79

—

4.82

11.03

1.42

7.36

1.64

1.45

—

3.63

9.18

0.71

5.91

1.29

1.14

—

3.23

9.68

0.50

7.06

1.00

0.89

—

Input FF/Latch Hold Timing:

Pad from ExpressCLK (fast-capture latch/FF)

Pad Delayed from ExpressCLK

(fast-capture latch/FF)

Pad from Clock (input latch/FF)

Pad Delayed from Clock (input latch/FF)

Clock Enable from Clock (CE from CLK)

Local Set/Reset (sync) from Clock

(LSR from CLK)

INREGE_HLD

INREGED_HLD

INREG_HLD

INREGD_HLD

INCE_HLD

INLSR_HLD

0.00

—

0.00

—

0.00

—

0.00

—

Clock-to-in Delay (FF CLK to IN1, IN2)

Clock-to-in Delay (latch CLK to IN1, IN2)

Local S/R (async) to IN (LSR to IN1, IN2)

LatchFF in Latch Mode

Global S/R to In (GSRN to IN1, IN2)

INREG_DEL

INLTCH_DEL

INLSR_DEL

INLSRL_DEL

INGSR_DEL

—

4.05

4.08

6.11

5.89

5.38

—

3.14

3.19

4.76

4.66

4.22

—

2.53

2.62

3.81

3.57

3.44

—

2.05

2.14

3.17

2.98

2.88

Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns.

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