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OR3C80 Datasheet(PDF) 110 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 110 Page - Agere Systems |
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110 / 210 page ![]() 110 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 45. Synchronous Memory Read Characteristics OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same timing parameter and may accurately report delays that are less than those listed. 5-4622(F) Figure 66. Synchronous Memory Read Cycle Parameter (TJ = 85 °C, VDD = min) Symbol Speed Unit -4 -5 -6 -7 Min Max Min Max Min Max Min Max Read Operation: Data Valid After Address (Kz[3:0] to F[6, 4, 2, 0]) Data Valid After Address (F5[A:D] to F[6, 4, 2, 0]) RA_DEL RA4_DEL — — 2.34 2.11 — — 1.80 1.57 — — 1.32 1.23 — — 1.05 0.99 ns ns Read Operation, Clocking Data into Latch/FF: Address to Clock Setup Time (Kz[3:0] to CLK) Address to Clock Setup Time (F5[A:D] to CLK) Address from Clock Hold Time (Kz[3:0] from CLK) Address from Clock Hold Time (F5[A:D] from CLK) Clock to PFU Output—Register (CLK to Q[6, 4, 2, 0]) Read Cycle Delay RA_SET RA4_SET RA_HLD RA4_HLD REG_DEL SMRD_CYC 1.99 1.79 0.00 0.00 — — — — — — 2.38 10.48 1.47 1.33 0.00 0.00 — — — — — — 1.75 7.66 1.08 1.03 0.00 0.00 — — — — — — 1.26 7.53 0.85 0.81 0.00 0.00 — — — — — — 0.97 5.78 ns ns ns ns ns ns Kz[3:0], F5[A:D] F[6, 4, 2, 0] CLK Q[3:0] RA_DEL RA4_DEL RA_SET RA4_SET REG_DEL RA_HLD RA4_HLD SMRD_CYC |
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