OR3C80 datasheet(106/210 Pages) AGERE

106 / 210 page

106

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

Table 42. Sequential PFU Timing Characteristics

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Parameter

Symbol

Speed

Unit

-4

-5

-6

-7

Min Max

Min Max Min Max Min Max

Input Requirements

Clock Low Time

CLKL_MPW

3.36

—

2.07

—

0.94

—0.72—

Clock High Time

CLKH_MPW

1.61

—

1.06

—

0.54

—0.45—

Global S/R Pulse Width (GSRN)

GSR_MPW

3.36

—

2.07

—

0.94

—0.72—

Local S/R Pulse Width

LSR_MPW

3.36

—

2.07

—

0.94

—0.72—

Combinatorial Setup Times (TJ = +85 °C, VDD = min):

Four-input Variables to Clock (Kz[3:0] to CLK)*

Five-input Variables to Clock (F5[A:D] to CLK)

Data In to Clock (DIN[7:0] to CLK)

Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK)

Clock Enable to Clock (CE to CLK)

Clock Enable to Clock (ASWE to CLK)

Local Set/Reset to Clock (SYNC) (LSR to CLK)

Data Select to Clock (SEL to CLK)

Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*

Two-level LUT to Clock (F5[A:D] to CLK w/feedbk)

Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*

Three-level LUT to Clock (F5[A:D] to CLK w/feedbk)

F4_SET

F5_SET

DIN_SET

CINDIR_SET

CE1_SET

CE2_SET

LSR_SET

SEL_SET

SWL2_SET

SWL2F5_SET

SWL3_SET

SWL3F5_SET

1.99

1.79

0.47

1.25

2.86

1.68

1.86

1.37

3.98

4.06

6.49

6.39

—

1.47

1.33

0.32

0.99

2.15

1.30

1.36

1.00

2.99

2.97

4.81

4.73

—

1.08

1.03

0.18

0.71

1.80

0.95

0.86

0.92

2.13

2.29

3.42

3.34

—

0.85

0.81

0.16

0.58

1.37

0.77

0.68

0.70

1.63

1.68

2.64

2.57

—

Combinatorial Hold Times (TJ = all, VDD = all):

Data In (DIN[7:0] from CLK)

Carry-in from Clock, DIRECT to REGCOUT (CIN from

CLK)

Clock Enable (CE from CLK)

Clock Enable from Clock (ASWE from CLK)

Local Set/Reset from Clock (sync) (LSR from CLK)

Data Select from Clock (SEL from CLK)

All Others

DIN_HLD

CINDIR_HLD

CE1_HLD

CE2_HLD

LSR_HLD

SEL_HLD

—

0.00

—

0.00

—

0.00

—

0.00

—

Output Characteristics

Sequential Delays (TJ = +85 °C, VDD = min):

Local S/R (async) to PFU Out (LSR to Q[7:0], REG-

COUT)

Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT)

Clock to PFU Out—Register (CLK to Q[7:0], REG-

COUT)

Clock to PFU Out—Latch (CLK to Q[7:0])

Transparent Latch (DIN[7:0] to Q[7:0])

LSR_DEL

GSR_DEL

REG_DEL

LTCH_DEL

LTCHD_DEL

—

7.02

5.21

2.38

2.51

2.73

—

5.29

3.90

1.75

1.88

2.10

—

3.64

2.55

1.26

1.21

1.38

—

2.90

2.00

0.97

0.96

1.12

* Four-input variables’ (KZ[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.

Note: The table shows worst-case delays. ORCA Foundry reports the delays for individual paths within a group of paths representing the same

timing parameter and may accurately report delays that are less than those listed.

OR3C80 Datasheet(PDF) 106 Page - Agere Systems

OR3C80 Datasheet(HTML) 106 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL