OR3C80 datasheet(104/210 Pages) AGERE

104 / 210 page

104

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Timing Characteristics (continued)

In addition to supply voltage, process variation, and

operating temperature, circuit and process improve-

ments of the

ORCA Series FPGAs over time will result

in significant improvement of the actual performance

over those listed for a speed grade. Even though lower

speed grades may still be available, the distribution of

yield to timing parameters may be several speed

grades higher than that designated on a product brand.

Design practices need to consider best-case timing

parameters (e.g., delays = 0), as well as worst-case

timing.

The routing delays are a function of fan-out and the

capacitance associated with the CIPs and metal inter-

connect in the path. The number of logic elements that

can be driven (fan-out) by PFUs is unlimited, although

the delay to reach a valid logic level can exceed timing

requirements. It is difficult to make accurate routing

delay estimates prior to design compilation based on

fan-out. This is because the CAE software may delete

redundant logic inserted by the designer to reduce fan-

out, and/or it may also automatically reduce fan-out by

net splitting.

The waveform test points are given in the Input/Output

Buffer Measurement Conditions section of this data

sheet. The timing parameters given in the electrical

characteristics tables in this data sheet follow industry

practices, and the values they reflect are described

below.

Propagation Delay—The time between the specified

reference points. The delays provided are the worst

case of the tphh and tpll delays for noninverting func-

tions, tplh and tphl for inverting functions, and tphz and

tplz for 3-state enable.

Setup Time—The interval immediately preceding the

transition of a clock or latch enable signal, during which

the data must be stable to ensure it is recognized as

the intended value.

Hold Time—The interval immediately following the

transition of a clock or latch enable signal, during which

the data must be held stable to ensure it is recognized

as the intended value.

3-State Enable—The time from when a 3-state control

signal becomes active and the output pad reaches the

high-impedance state.

PFU Timing

* Four-input variables’ (KZ[3:0]) path delays are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.

Table 41. Combinatorial PFU Timing Characteristics

OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C

< TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.

OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C

< TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C.

Parameter

Symbol

Speed

Unit

-4

-5

-6

-7

Min Max Min

Max

Min

Max

Min

Max

Combinatorial Delays (TJ = +85 °C, VDD = min):

Four-input Variables (Kz[3:0] to F[z])*

Five-input Variables (F5[A:D] to F[0, 2, 4, 6])

Two-level LUT Delay (Kz[3:0] to F w/feedbk)*

Two-level LUT Delay (F5[A:D] to F w/feedbk)

Three-level LUT Delay (Kz[3:0] to F w/feedbk)*

Three-level LUT Delay (F5[A:D] to F w/feedbk)

CIN to COUT Delay (logic mode)

F4_DEL

F5_DEL

SWL2_DEL

SWL2F5_DEL

SWL3_DEL

SWL3F5_DEL

CO_DEL

—

2.34

2.11

4.87

4.69

6.93

6.89

3.47

—

1.80

1.57

3.66

3.51

5.15

5.08

2.65

—

1.32

1.23

2.58

2.48

3.63

3.54

1.79

—

1.05

0.99

2.03

1.94

2.82

2.75

1.43

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