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OR3C80 Datasheet(PDF) 114 Page - Agere Systems |
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OR3C80 Datasheet(HTML) 114 Page - Agere Systems |
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114 / 210 page  114 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 48. Programmable I/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial: VDD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C. OR3Txxx Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C < TA < +85 °C. Parameter Symbol Speed Unit -4 -5 -6 -7 Min Max Min Max Min Max Min Max PIO Logic Block Delays Out to Pad (OUT[2:1] via logic to pad): Fast Slewlim Sinklim OUTLF_DEL OUTLSL_DEL OUTLSI_DEL — — — 5.09 7.86 9.41 — — — 4.21 6.49 7.98 — — — 2.63 3.49 8.08 — — — 2.17 2.91 7.32 ns ns ns Outreg to Pad (OUTREG via logic to pad): Fast Slewlim Sinklim OUTRF_DEL OUTRSL_DEL OUTRSI_DEL — — — 6.71 9.47 11.03 — — — 5.44 7.71 9.20 — — — 3.56 4.42 8.98 — — — 2.78 3.52 7.94 ns ns ns Clock to Pad (ECLK, CLK via logic to pad): Fast Slewlim Sinklim OUTCF_DEL OUTCSL_DEL OUTCSI_DEL — — — 6.97 9.74 11.29 — — — 5.68 7.96 9.45 — — — 3.71 4.57 9.13 — — — 2.91 3.64 8.07 ns ns ns 3-State FF Delays 3-state Enable/Disable Delay (TS direct to pad): Fast Slewlim Sinklim TSF_DEL TSSL_DEL TSSI_DEL — — — 4.93 7.70 9.25 — — — 4.09 6.37 7.86 — — — 2.33 3.00 7.95 — — — 1.88 2.41 7.23 ns ns ns Local Set/Reset (async) to Pad (LSR to pad): Fast Slewlim Sinklim TSLSRF_DEL TSLSRSL_DEL TSLSRSI_DEL — — — 8.25 11.01 12.57 — — — 6.65 8.92 10.41 — — — 4.24 4.92 9.87 — — — 3.39 3.92 8.74 ns ns ns Global Set/Reset to Pad (GSRN to pad): Fast Slewlim Sinklim TSGSRF_DEL TSGSRSL_DEL TSGSRSI_DEL — — — 7.52 10.28 11.84 — — — 6.09 8.36 9.85 — — — 3.88 4.55 9.51 — — — 3.11 3.64 8.45 ns ns ns 3-State FF Setup Timing: TS to ExpressCLK (TS to ECLK) TS to Clock (TS to CLK) Local Set/Reset (sync) to Clock (LSR to CLK) TSE_SET TS_SET TSLSR_SET 0.00 0.00 0.28 — — — 0.00 0.00 0.21 — — — 0.00 0.00 0.17 — — — 0.00 0.00 0.18 — — — ns ns ns 3-State FF Hold Timing: TS from ExpressCLK (TS from ECLK) TS from Clock (TS from CLK) Local Set/Reset (sync) from Clock (LSR from CLK) TSE_HLD TS_HLD TSLSR_HLD 0.85 0.85 0.00 — — — 0.68 0.68 0.00 — — — 0.44 0.44 0.00 — — — 0.34 0.34 0.00 — — — ns ns ns Clock to Pad Delay (ECLK, SCLK to pad): Fast Slewlim Sinklim TSREGF_DEL TSREGSL_DEL TSREGSI_DEL — — — 5.94 8.70 10.26 — — — 4.82 7.10 8.59 — — — 2.84 3.52 8.47 — — — 2.23 2.76 7.58 ns ns ns Note: The delays for all input buffers assume an input rise/fall time of <1 V/ns. |
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