OR3C80 datasheet(154/210 Pages) AGERE

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154

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Pin Information (continued)

Compatibility with OR2C/TxxA Series

The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices

offered in the same packages. This includes the following pins: VDD, VSS, VDD5 (OR2TxxA Series only), and all

configuration pins.

The following restrictions apply:

1. There are two configuration modes supported in the OR2C/TxxA Series that are not supported in Series 3: mas-

ter parallel down and synchronous peripheral modes. The Series 3 FPGAs have two new microprocessor inter-

face (MPI) configuration modes that are unavailable in the OR2C/TxxA Series.

2. There are four pins—one per each device side—that are user I/O in the OR2C/TxxA Series which can only be

used as fast dedicated clocks or global inputs in Series 3. These pins are also used to drive the ExpressCLK to

the I/O FFs on their given side of the device. These four middle ExpressCLK pins should not be used to connect

to a programmable clock manager (PCM). A corner ExpressCLK input should be used instead (see item 3

below). See Table 69 for a list of these pins in each package.

3. There are two other pins that are user I/O in both the OR2C/TxxA and Series 3 but also have optional added

functionality. Each of these pins drives the ExpressCLKs on two sides of the device. They also have fast connec-

tivity to the programmable clock manager (PCM). See Table 69 for a list of these pins in each package.

Table 69. Series 3 ExpressCLK Pins

Pin Name/

Package

208-Pin

SQFP/SQFP2

240-Pin

SQFP/SQFP2

256-Pin

PBGA

352-Pin

PBGA

432-Pin

EBGA

600-Pin

EBGA

I-ECKL

R29

U33

I-ECKB

W11

AE14

AH16

AM18

I-ECKR

131

152

K18

N23

I-ECKT

178

207

B11

B14

C15

C17

I/O-SECKLL

AB4

AG29

AK34

I/O-SECKUR

159

184

A19

A25

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