OR3C80 datasheet(152/210 Pages) AGERE

152 / 210 page

152

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Special-Purpose Pins (continued)

A11/MPI_IRQ

I/O

MPI

active-low interrupt request output.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

A10/MPI_BI

I/O

PowerPC mode MPI burst inhibit output.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

A9/MPI_ACK

I/O

In PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA) output. For

i960 MPI operation, it is the active-low ready/record (RDYRCV) output.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

A8/MPI_RW

I/O

In PowerPC mode MPI operation, this is the active-low write/active-high read control signals.

For i960 operation, it is the active-high write/active-low read control signal.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

A7/MPI_CLK

I/O

This is the clock used for the synchronous MPI interface. For PowerPC, it is the CLKOUT

signal. For i960, it is the system clock that is chosen for the i960 external bus interface.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

A[4:0]

I/O

For PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in

PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note

that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in i960 MPI mode.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

A[1:0]/

MPI_BE[1:0]

I/O

For i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are used as

address bits A[1:0] in i960 byte-wide operation.

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).

D[7:0]

I/O

During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive

configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0

is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the

address/data pins for i960 microprocessor mode.

After configuration, the pins are user-programmable I/O pins (see Note).

DIN

I/O

During slave serial or master serial configuration modes, DIN accepts serial configuration

data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-

ing configuration, a pull-up is enabled.

After configuration, this pin is a user-programmable I/O pin (see Note).

DOUT

I/O

During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained

slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.

After configuration, DOUT is a user-programmable I/O pin (see Note).

Pin Information (continued)

Table 67. Pin Descriptions (continued)

Symbol

I/O

Description

Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE

release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the

activation of all user I/Os) is controlled by a second set of options.

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