OR3C80 datasheet(207/210 Pages) AGERE

207 / 210 page

Lucent Technologies Inc.

207

Data Sheet

June 1999

ORCA Series 3C and 3T FPGAs

Index

Absolute Maximum Ratings, 96

AND-OR-INVERT (AOI), 6

AND-OR-INVERT (AOI),1

(see also Supplemental Logic

Interconnect Cell (SLIC), 1

Architecture

Overview, 6—9

ASWE, 9, 11, 15—17, 23, 33, 48

Bidirectional Buffers (BIDIs), 6, 19, 43, 83

(see also Routingand SLIC)

Bit Stream (see FPGA Configuration)

Bit Stream Error Checking, 88

(see also FPGA states of Operation)

Boundary Scan, 55

(see Special Function Blocks)

Clock Control (CLKCNTRL), 50

(see also Clock Distribution Network and

Special Function Blocks)

Clock Distribution Network, 48–51

CLKCNTRL, 50

ExpressCLK, 48

Inputs, 51

Fast Clock, 48, 51

Global Control Signals, 48

In the PICs

ExpressCLK, 50

System Clock, 50

In the PLC Array

Fast Clock, 49

System Clock, 49

PFU Clock Sources, 48

Selecting Clock Input Pins, 51

System Clock, 48

To the PLC Array

Fast Clock, 50

System Clock, 50

Clock Enable (CE), 9, 11, 17, 23, 31, 48

Clock Multiplication (see PCM)

Comparator (see LUT Operating Modes)

Configuration (see FPGA States of Operation

or FPGA Configuration)

Control Inputs (see PICs, Inputs)

Demultiplexing (see PICs, Input Demultiplexing), 38

Duty-Cycle Adjustment (see PCM)

Electrical Characteristics, 97, 98

Error Checking (see FPGA Configuration)

ExpressCLK, 1, 6, 31, 34, 37, 39, 41, 43, 47—51,

70—74, 77—81

(see also Clock distribution Network and

Programmable Clock Manager)

Fast Clock, 46—51, 54

(see Clock Distribution Network)

5 V Tolerant I/O 35

Flexible Input Structure (FINS) 1, 27, 32

(see also Routing)

FPGA Configuration, 87—94

Configuration Frame Format, 87

Configuration Modes, 89

Asynchronous Peripheral Mode, 91

Daisy-Chaining, 95

Master Parallel Mode, 89

Master Serial Mode, 90

Microprocessor Interface (MPI) Mode, 91

Slave Parallel Mode, 94

Slave Serial Mode, 94

Data Format, 86

Data Frame, 86

Using

ORCA Foundry to Generate RAM Data, 86

FPGA States of Operation

Configuration, 83

Initialization, 82

Other Configuration Options, 85

Partial Reconfiguration, 85

Reconfiguration, 85

Start-Up, 84

IEEE Standard, 1149.1 55, 59

Initialization (see FPGA States of Operation)

Input/Output Buffers

Measurement Conditions, 138

Output Buffer Characteristics

OR3Cxx, 139

OR3Txxx, 141

JTAG (see Boundry Scan)

OR3C80 Datasheet(PDF) 207 Page - Agere Systems

OR3C80 Datasheet(HTML) 207 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL