S25FS256S datasheet(107/154 Pages) SPANSION

107 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

107

Da ta

Shee t

(Prelim i nar y )

length of the next Dual I/O Read command through the inclusion or exclusion of the first byte instruction code.

The lower nibble (bits 3-0) of the Mode bits are “don’t care” (“x”) and may be high impedance. If the Mode bits

equal Axh, then the device remains in Dual I/O Continuous Read mode and the next address can be entered

(after CS# is raised high and then asserted low) without the BBh or BCh instruction, as shown in Figure 10.31

on page 108; thus, eliminating eight cycles of the command sequence. The following sequences will release

the device from Dual I/O Continuous Read mode; after which, the device can accept standard SPI

commands:

1. During the Dual I/O Continuous Read command sequence, if the Mode bits are any value other

than Axh, then the next time CS# is raised high the device will be released from Dual I/O con ti no

us read mode.

2. Send the Mode Reset command.

Note that the four mode bit cycles are part of the device’s internal circuitry latency time to access the initial

address after the last address cycle that is clocked into IO0 (SI) and IO1 (SO).

It is important that the I/O signals be set to high-impedance at or before the falling edge of the first data out

clock. At higher clock speeds the time available to turn off the host outputs before the memory device begins

to drive (bus turn around) is diminished. It is allowed and may be helpful in preventing I/O signal contention,

for the host system to turn off the I/O signal outputs (make them high impedance) during the last two “don’t

care” mode cycles or during any dummy cycles.

Following the latency period the memory content, at the address given, is shifted out two bits at a time

through IO0 (SI) and IO1 (SO). Two bits are shifted out at the SCK frequency at the falling edge of SCK

signal.

The address can start at any byte location of the memory array. The address is automatically incremented to

the next higher address in sequential order after each byte of data is shifted out. The entire memory can

therefore be read out with one single read instruction and address 000000h provided. When the highest

address is reached, the address counter will wrap around and roll back to 000000h, allowing the read

sequence to be continued indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.

Figure 10.29 Dual I/O Read Command Sequence (3-Byte Address, BBh [CR2V[7]=0])

Note:

1. Least significant 4 bits of Mode are don’t care and it is optional for the host to drive these bits. The host may turn off drive during these

cycles to increase bus turn around time between Mode bits from host and returning data from the memory.

Figure 10.30 Dual I/O Read Command Sequence (4-Byte Address, BBh [CR2V[7]=1])

CS#

SCK

IO0

IO1

Phase

Instruction

Address

Mode

Dum

Data1

Data2

CS#

SCK

IO0

IO1

Phase

Instruction

Address

Mode

Dum

Data1

Data2

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