AMD-K6 datasheet(103/346 Pages) AMD

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Chapter 5

Signal Descriptions

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

5.8

BE[7:0]# (Byte Enables)

Output

Summary

BE[7:0]# are used by the processor to indicate the valid data

bytes during a write cycle and the requested data bytes during

a read cycle. The byte enables can be used to derive address bits

A[2:0], which are not physically part of the processor’s address

bus. The processor checks and generates valid data parity for

the data bytes that are valid as defined by the byte enables. The

eight byte enables correspond to the eight bytes of the data bus

as follows:

The processor expects data to be driven by the system logic on

all eight bytes of the data bus during a burst cache-line read

cycle, independent of the byte enables that are asserted.

The byte enables are also used to distinguish between special

bus cycles as defined in Table 19 on page 119.

Driven and Floated

BE[7:0]# are driven off the same clock edge as ADS # and

remain in the same state until the clock edge on which NA# or

the last expected BRDY # of the cycle is sampled asserted.

BE[7:0]# are driven during memory cycles, I/O cycles, special

bus cycles, and interrupt acknowledge cycles.

The processor floats BE[7:0]# off the clock edge that BOFF# is

sampled asserted and off the clock edge that the processor

asserts HLDA in recognition of HOLD. Unlike the address bus,

BE[7:0]# are not floated in response to AHOLD.

BE7#: D[63:56]

BE3#: D[31:24]

BE6#: D[55:48]

BE2#: D[23:16]

BE5#: D[47:40]

BE1#: D[15:8]

BE4#: D[39:32]

BE0#: D[7:0]

AMD-K6 Datasheet(PDF) 103 Page - Advanced Micro Devices