AMD-K6 datasheet(143/346 Pages) AMD

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Chapter 6

Bus Cycles

125

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

sampled asserted). If the last BRDY# is not sampled asserted,

the processor enters the Pipeline Data state.

If the processor samples the last BRDY# asserted in this state, it

determines if a bus transition is required between the current

bus cycle and the pipelined bus cycle. A bus transition is

required when the data bus direction changes between bus

cycles, such as a memory write cycle followed by a memory read

cycle. If a bus transition is required, the processor enters the

Transition state for one clock to prevent data bus contention. If

a bus transition is not required, the processor enters the Data

state.

The processor does not transition to the Data-NA# Requested

state from the Pipeline Address state because the processor

does not begin sampling NA# until it has exited the Pipeline

Address state.

Pipeline Data

Two bus cycles are concurrently executing in this state. The

processor cannot issue any additional bus cycles until the

current bus cycle is completed. The processor drives the data

bus during write cycles or expects data to be returned during

read cycles for the current bus cycle until the last BRDY# of the

current bus cycle is sampled asserted.

If the processor samples the last BRDY# asserted in this state, it

determines if a bus transition is required between the current

bus cycle and the pipelined bus cycle. If the bus transition is

required, the processor enters the Transition state for one clock

to prevent data bus contention. If a bus transition is not

required, the processor enters the Data state (NA# was not

sampled asserted) or the Data-NA# Requested state (NA# was

sampled asserted).

Transition

The processor enters this state for one clock during data bus

transitions and enters the Data state on the next clock edge if

NA# is not sampled asserted. The sole purpose of this state is to

avoid bus contention caused by bus transitions during pipeline

operation.

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