AMD-K6 datasheet(139/346 Pages) AMD

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Chapter 6

Bus Cycles

121

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Bus Cycles

The following sections describe and illustrate the timing and

relationship of bus signals during various types of bus cycles. A

representative set of bus cycles is illustrated.

6.1

Timing Diagrams

The timing diagrams illustrate the signals on the external local

bus as a function of time, as measured by the bus clock (CLK).

Throughout this chapter, the term clock refers to a signal

bus-clock cycle. A clock extends from one rising CLK edge to

the next rising CLK edge. The processor samples and drives

most signals relative to the rising edge of CLK. The exceptions

to this rule include the following:

BF[2:0]—Sampled on the falling edge of RESET

FLUSH#, BRDYC#—Sampled on the falling edge of RESET,

also sampled on the rising edge of CLK

All inputs and outputs are sampled relative to TCK in

Boundary-Scan Test Mode. Inputs are sampled on the rising

edge of TCK, outputs are driven off of the falling edge of

TCK.

For each signal in the timing diag rams, the High level

represents 1, the Low level represents 0, and the Middle level

represents the floating (high-impedance) state. When both the

High and Low levels are shown, the meaning depends on the

signal. A single signal indicates ‘don’t care’. In the case of bus

activity, if both High and Low levels are shown, it indicates the

processor, alternate master, or system logic is driving a value,

but this value may or may not be valid. (For example, the value

on the address bus is valid only during the assertion of ADS#,

but addresses are also driven on the bus at other times.) Figure

43 on page 122 defines the different waveform representations.

AMD-K6 Datasheet(PDF) 139 Page - Advanced Micro Devices