AMD-K6 datasheet(144/346 Pages) AMD

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126

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

6.3

Memory Reads and Writes

The AMD-K6 processor performs single or burst memory bus

cycles. The single-transfer memory bus cycle transfers 1, 2, 4, or

8 bytes and requires a minimum of two clocks. Misaligned

instructions or operands result in a split cycle, which requires

multiple transactions on the bus. A burst cycle consists of four

back-to-back 8-byte (64-bit) transfers on the data bus.

Single-Transfer

Memory Read and

Write

Figure 45 on page 127 shows a single-transfer read from memory,

followed by two single-transfer writes to memory. For the

memory read cycle, the processor asserts ADS# for one clock to

validate the bus cycle and also drives A[31:3], BE[7:0]#, D/C#,

W/R#, and M/IO# to the bus. The processor then waits for the

system logic to return the data on D[63:0] (with DP[7:0] for

parity checking) and assert BRDY#. The processor samples

BRDY# on every clock edge starting with the clock edge after

the clock edge that negates ADS#. See “BRDY# (Burst Ready)”

on page 88.

During the read cycle, the processor drives PCD, PWT, and

CACHE# to indicate its caching and cache-coherency intent for

the access. The system logic returns KEN# and WB/WT# to

either confirm or change this intent. If the processor asserts

PCD and negates CACHE#, the accesses are non-cacheable,

even though the system logic asserts KEN# during the BRDY#

to indicate its support for cacheability. The processor (which

drives CACHE#) and the system logic (which drives KEN#) must

agree in order for an access to be cacheable.

The processor can drive another cycle (in this example, a write

cycle) by asserting ADS# off the next clock edge after BRDY# is

sampled asserted. Therefore, an idle clock is guaranteed

between any two bus cycles. The processor drives D[63:0] with

valid data one clock edge after the clock edge on which ADS# is

asserted. To minimize CPU idle times, the system logic stores the

address and data in write buffers, returns BRDY#, and performs

the store to memory later. If the processor samples EWBE#

negated during a write cycle, it suspends certain activities until

EWBE# is sampled asserted. See “EWBE# (External Write

Buffer Empty)” on page 95. In Figure 45, the second write cycle

occurs during the execution of a serializing instruction. The

processor delays the following cycle until EWBE# is sampled

asserted.

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