AMD-K6 datasheet(160/346 Pages) AMD

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142

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

AHOLD-Initiated

Inquire Miss

AHOLD can be asserted by the system to initiate one or more

inquire cycles. To allow the system to drive the address bus

during an inquire cycle, the processor floats A[31:3] and AP off

the clock edge on which AHOLD is sampled asserted. The data

bus and all other control and status signals remain under the

control of the processor and are not floated. This functionality

allows a bus cycle in progress when AHOLD is sampled asserted

to continue to completion. The processor resumes driving the

address bus off the clock edge on which AHOLD is sampled

negated.

In Figure 54 on page 143, the processor samples AHOLD

asserted during the memory burst read cycle, and it floats the

address bus off the same clock edge on which it samples AHOLD

asserted. While the processor still controls the bus, it completes

the current cycle until the last expected BRDY# is sampled

asserted. The system logic drives EADS# with an inquire

address on A[31:5] during an inquire cycle. The processor

samples EADS# asserted and compares the inquire address to

its tag address in both the instruction and data caches. In Figure

54, the inquire address misses the tag address in the processor

(both HIT# and HITM# are negated). Therefore, the processor

proceeds to the next cycle when it samples AHOLD negated.

(The processor can drive a new cycle by asserting ADS# off the

same clock edge that it samples AHOLD negated.)

For an AHOLD-initiated inquire cycle to be recognized, the

processor must sample AHOLD asserted for at least two

consecutive clocks before it samples EADS# asserted. If the

processor detects an address parity error during an inquire

cycle, APCHK# is asserted for one clock. The system logic must

respond appropriately to the assertion of this signal.

AMD-K6 Datasheet(PDF) 160 Page - Advanced Micro Devices