AMD-K6 datasheet(158/346 Pages) AMD

158 / 346 page

140

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

HOLD-Initiated

Inquire Hit to

Modified Line

Figure 53 on page 141 shows the same sequence as Figure 52 on

page 139, but in Figure 53 the inquire cycle hits a modified line

and the processor asserts both HIT# and HITM#. In this

example, the processor performs a writeback cycle immediately

after the inquire cycle. It updates the modified cache line to the

external memory (normally, level-two cache or DRAM). The

processor uses the address (A[31:5]) that was latched during the

inquire cycle to perform the writeback cycle. The processor

asserts HITM# throughout the writeback cycle and negates

HITM# one clock edge after the last expected BRDY# of the

writeback is sampled asserted.

When the processor samples EADS# during the inquire cycle, it

also samples INV to determine the cache line MESI state after

the inquire cycle. If INV is sampled asserted during an inquire

cycle, the processor transitions the line (if found) to the invalid

stat e, regardless of its prev ious sta te. Th e c a ch e line

invalidation operation is not visible on the bus. If INV is

sampled negated during an inquire cycle, the processor

transitions the line (if found) to the shared state. In Figure 53

the processor samples INV asserted during the inquire cycle.

In a HOLD-initiated inquire cycle, the system logic can negate

HOLD off the same clock edge on which EADS# is sampled

asserted. The processor drives HIT# and HITM# on the clock

edge after the clock edge on which EADS# is sampled asserted.

AMD-K6 Datasheet(PDF) 158 Page - Advanced Micro Devices