AMD-K6 datasheet(156/346 Pages) AMD

156 / 346 page

138

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

HOLD-Initiated

Inquire Hit to Shared

or Exclusive Line

Figure 52 on page 139 shows a HOLD-initiated inquire cycle. In

this example, the processor samples HOLD asserted during the

burst memory read cycle. The processor completes the current

cycle (until the last expected BRDY# is sampled asserted),

asserts HLDA and floats its outputs as described on page 136.

The system logic drives an inquire cycle within the hold

acknowledge cycle. It asserts EADS#, which validates the

inquire address on A[31:5]. If EADS# is sampled asserted

before HOLD is sampled negated, the processor recognizes it as

a valid inquire cycle.

In Figure 52, the processor asserts HIT# and negates HITM# on

the clock edge after the clock edge on which EADS# is sampled

asserted, indicating the current inquire cycle hit a shared or

exclusive cache line. (Shared and exclusive cache lines in the

processor data or instruction cache have the same contents as

the data in the external memory.) During an inquire cycle, the

processor samples INV to determine whether the addressed

cache line found in the processor’s instruction or data cache

transitions to the invalid state or the shared state. In this

example, the processor samples INV asserted with EADS#,

which invalidates the cache line.

The system logic can negate HOLD off the same clock edge on

which EADS# is sampled asserted. The processor continues

driving HIT# in the same state until the next inquire cycle.

HITM# is not asserted unless HIT# is asserted.

AMD-K6 Datasheet(PDF) 156 Page - Advanced Micro Devices