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AMD-K6 Datasheet(PDF) 153 Page - Advanced Micro Devices |
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AMD-K6 Datasheet(HTML) 153 Page - Advanced Micro Devices |
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153 / 346 page  Chapter 6 Bus Cycles 135 20695H/0—March 1998 AMD-K6® Processor Data Sheet Preliminary Information Misaligned I/O Read and Write Table 22 shows the misaligned I/O read and write cycle order executed by the AMD-K6. In Figure 50, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant bytes (MSBs) to complete the misaligned bus cycle. Figure 50. Misaligned I/O Transfer Table 22. Bus-Cycle Order During Misaligned I/O Transfers Type of Access First Cycle Second Cycle I/O Read LSBs MSBs I/O Write LSBs MSBs LSB MSB LSB MSB Misaligned I/O Read Misaligned I/O Write CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] BRDY# ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE LOCK# SCYC |
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