AMD-K6 datasheet(154/346 Pages) AMD

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136

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

6.5

Inquire and Bus Arbitration Cycles

The AMD-K6 processor provides built-in level-one data and

instruction caches. Each cache is 32 Kbytes and two-way

set-associative. The system logic or other bus master devices

can initiate an inquire cycle to maintain cache/memory

coherency. In response to the inquire cycle, the processor

compares the inquire address with its cache tag addresses in

both caches, and, if necessary, updates the MESI state of the

cache line and performs writebacks to memory.

An inquire cycle can be initiated by asserting AHOLD, BOFF#,

or HOLD. AHOLD is exclusively used to support inquire cycles.

During AHOLD-initiated inquire cycles, the processor only

floats the address bus. BOFF# provides the fastest access to the

bus because it aborts any processor cycle that is in-progress,

whereas AHOLD and HOLD both permit an in-progress bus

cycle to complete. During HOLD-initiated and BOFF#-initiated

inquire cycles, the processor floats all of its bus-driving signals.

Hold and Hold

Acknowledge Cycle

The system logic or another bus device can assert HOLD to

initiate an inquire cycle or to gain full control of the bus. When

the AMD-K6 processor samples HOLD asserted, it completes

any in-progress bus cycle and asserts HLDA to acknowledge

release of the bus. The processor floats the following signals off

the same clock edge that HLDA is asserted:

Figure 51 on page 137 shows a basic HOLD/HLDA operation. In

this example, the processor samples HOLD asserted during the

memory read cycle. It continues the current memory read cycle

until BRDY# is sampled asserted. The processor drives HLDA

and floats its outputs one clock edge after the last BRDY# of the

cycle is sampled asserted. The system logic can assert HOLD for

as long as it needs to utilize the bus. The processor samples

HOLD on every clock edge but does not assert HLDA until any

in-progress cycle or sequence of locked cycles is completed.

A[31:3]

DP[7:0]

ADS#

LOCK#

AP#

M/IO#

BE[7:0]#

PCD

CACHE#

PWT

D[63:0]

SCYC

D/C#

W/R#

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