AMD-K6 datasheet(150/346 Pages) AMD

150 / 346 page

132

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Burst Writeback

Figure 48 on page 133 shows a burst read followed by a

writeback transaction. The AMD-K6 processor initiates

writebacks under the following conditions:

Replacement —If a cache-line fill is initiated for a cache line

currently filled with valid entries, the processor uses a

least-recently-allocated (LRA) algorithm to select a line for

replacement. Before a replacement is made to a data cache

line that is in the modified state, the modified line is

scheduled to be written back to memory.

Internal Snoop—The processor snoops the data cache

whenever an instruction-cache line is read, and it snoops the

instruction cache whenever a data cache line is written. This

snooping is performed to determine whether the same

address is stored in both caches, a situation that is taken to

imply the occurrence of self-modifying code. If a snoop hits a

data cache line in the modified state, the line is written back

to memory before being invalidated.

WBINVD Instruction—When the processor executes a

WBINVD instruction, it writes back all modified lines in the

data cache and then invalidates all lines in both caches.

Cache

Flush—When

the

processor

samples

FLUSH#

asserted, it executes a flush acknowledge special cycle and

writes back all modified lines in the data cache and then

invalidates all lines in both caches.

The processor drives writeback cycles during inquire or cache

flush cycles. The writeback shown in Figure 48 is caused by a

cache-line replacement. The processor completes the burst read

cycle that fills the cache line. Immediately following the burst

read cycle is the burst writeback cycle that represents the

modified line to be written back to memory. D[63:0] are driven

one clock edge after the clock edge on which ADS# is asserted

and are subsequently changed off the clock edge on which each

BRDY# assertion of the burst cycle is sampled.

AMD-K6 Datasheet(PDF) 150 Page - Advanced Micro Devices

AMD-K6 Datasheet(HTML) 150 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL