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Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

6.4

I/O Read and Write

Basic I/O Read and

Write

The processor accesses I/O when it executes an I/O instruction

(for example, IN or OUT). Figure 49 shows an I/O read followed

by an I/O write. The processor drives M/IO# Low and D/C# High

during I/O cycles. In this example, the first cycle shows a single

wait state I/O read cycle. It follows the same sequence as a

single-transfer memory read cycle. The processor drives ADS#

to initiate the bus cycle, then it samples BRDY# on every clock

edge starting with the clock edge after the clock edge that

negates ADS#. The system logic must return BRDY# to

complete the cycle. When the processor samples BRDY#

asserted, it can assert ADS# for the next cycle off the next clock

edge. (In this example, an I/O write cycle.)

The I/O write cycle is similar to a memory write cycle, but the

processor drives M/IO# low during an I/O write cycle. The

processor asserts ADS# to initiate the bus cycle. The processor

drives D[63:0] with valid data one clock edge after the clock

edge on which ADS# is asserted. The system logic must assert

BRDY# when the data is properly stored to the I/O destination.

The processor samples BRDY# on every clock edge starting with

the clock edge after the clock edge that negates ADS#. In this

example, two wait states are inserted while the processor waits

for BRDY# to be asserted.

Figure 49. Basic I/O Read and Write

I/O Read Cycle

I/O Write Cycle

CLK

A[31:3]

BE[7:0]#

ADS#

M/IO#

D/C#

W/R#

D[63:0]

BRDY#

ADDR

DATA

IDLE

ADDR

DATA

IDLE

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