AMD-K6 datasheet(170/346 Pages) AMD

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152

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Locked Cycles

The processor asserts LOCK# during a sequence of bus cycles to

ensure the cycles are completed without allowing other bus

masters to intervene. Locked operations can consist of two to

five cycles. LOCK# is asserted during the following operations:

An interrupt acknowledge sequence

Descriptor Table accesses

Page Directory and Page Table accesses

XCHG instruction

An instruction with an allowable LOCK prefix

In order to ensure that locked operations appear on the bus and

are visible to the entire system, any data operands addressed

during a locked cycle that reside in the processor’s cache are

flushed and invalidated from the cache prior to the locked

operation. If the cache line is in the modified state, it is written

back and invalidated prior to the locked operation. Likewise,

any data read during a locked operation is not cached. The

processor negates LOCK# for at least one clock between

consecutive sequences of locked operations to allow the system

logic to arbitrate for the bus.

The processor asserts SCYC during misaligned locked transfers

on the D[63:0] data bus. The processor generates additional bus

cycles to complete the transfer of misaligned data.

Basic Locked

Operation

Figure 59 on page 153 shows a pair of read-write bus cycles. It

represents a typical read-modify-write locked operation. The

processor asserts LOCK# off the same clock edge that it asserts

ADS# of the first bus cycle in the locked operation and holds it

asserted until the last expected BRDY# of the last bus cycle in

the locked operation is sampled asserted. (The processor

negates LOCK# off the same clock edge.)

AMD-K6 Datasheet(PDF) 170 Page - Advanced Micro Devices