AMD-K6 datasheet(174/346 Pages) AMD

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156

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

Interrupt

Acknowledge

In response to recognizing the system’s maskable interrupt

(INTR), the processor drives an interrupt acknowledge cycle at

the ne xt instru c t i o n boundar y. Dur i ng an inter r upt

acknowledge cycle, the processor drives a locked pair of read

cycles as shown in Figure 61 on page 157. The first read cycle is

not functional, and the second read cycle returns the interrupt

number on D[7:0] (00h–FFh). Table 23 shows the state of the

signals during an interrupt acknowledge cycle.

The system logic can drive INTR either synchronously or

asynchronously. If it is asserted asynchronously, it must be

asserted for a minimum pulse width of two clocks. To ensure it

is recognized, INTR must remain asserted until an interrupt

acknowledge sequence is complete.

Table 23. Interrupt Acknowledge Operation Definition

Processor Outputs

First Bus Cycle

Second Bus Cycle

D/C#

Low

M/IO#

Low

W/R#

Low

BE[7:0]#

EFh

FEh (low byte enabled)

A[31:3]

0000_0000h

D[63:0]

(ignored)

Interrupt number expected from interrupt

controller on D[7:0]

AMD-K6 Datasheet(PDF) 174 Page - Advanced Micro Devices