AMD-K6 datasheet(176/346 Pages) AMD

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158

Bus Cycles

Chapter 6

AMD-K6® Processor Data Sheet

20695H/0—March 1998

Preliminary Information

6.6

Special Bus Cycles

The AMD-K6 processor drives special bus cycles that include

stop grant, flush acknowledge, cache writeback invalidation,

halt, cache invalidation, and shutdown cycles. During all

special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and

A[31:3] are driven to differentiate among the special cycles, as

shown in Table 24. The system logic must return BRDY# in

response to all processor special cycles.

Basic Special Bus

Cycle

Figure 62 on page 159 shows a basic special bus cycle. The

processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same

clock edge that it asserts ADS#. In this example, BE[7:0]# = FBh

and A[31:3] = 0000_0000h, which indicates that the special

cycle is a halt special cycle (See Table 24). A halt special cycle is

generated after the processor executes the HLT instruction.

If the processor samples FLUSH# asserted, it writes back any

data cache lines that are in the modified state and invalidates

all lines in the instruction and data cache. The processor then

drives a flush acknowledge special cycle.

If the processor executes a WBINVD instruction, it drives a

wr iteback s pecial cy cle after the proces sor com plete s

invalidating and writing back the cache lines.

Table 24. Encodings For Special Bus Cycles

BE[7:0]#

A[4:3]*

Special Bus Cycle

Cause

FBh

10b

Stop Grant

STPCLK# sampled asserted

EFh

00b

Flush Acknowledge FLUSH# sampled asserted

F7h

00b

Writeback

WBINVD instruction

FBh

00b

Halt

HLT instruction

FDh

00b

Flush

INVD,WBINVD instruction

FEh

00b

Shutdown

Triple fault

Note:

A[31:5] = 0

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