28F128 datasheet(17/58 Pages) INTEL

17 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

NOTES:

1. See Table 2 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. DQ refers to DQ0–DQ7 if BYTE# is low and DQ0–DQ15 if BYTE# is high.

4. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered.

5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for

VPENLK and VPENH voltages.

6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit

configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with

programming inactive), program suspend mode, or reset/power-down mode.

7. High Z will be VOH with an external pull-up resistor.

8. See Section 3.6 for read identifier code data.

9. See Section 4.2 for read query data.

10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN =

VPENH and VCC is within specification.

11. Refer to Table 4 for valid DIN during a write operation.

Table 3.

Bus Operations

Mode

Notes

RP#

CE0,1,2

(1)

OE#(2)

WE#(2)

Address

VPEN

DQ(3)

STS

(default

mode)

Read Array

4,5,6

VIH

Enabled

VIL

VIH

DOUT

High Z(7)

Output Disable

VIH

Enabled

VIH

High Z

Standby

VIH

Disabled

High Z

Reset/Power-Down

Mode

VIL

High Z

High Z(7)

Read Identifier Codes

VIH

Enabled

VIL

VIH

See

Figure 5

Note 8

High Z(7)

Read Query

VIH

Enabled

VIL

VIH

See

Table 7

Note 9

High Z(7)

Read Status (WSM off)

VIH

Enabled

VIL

VIH

DOUT

Read Status (WSM on)

VIH

Enabled

VIL

VIH

DQ7 = DOUT

DQ15–8 = High Z

DQ6–0 = High Z

Write

6,10,11

VIH

Enabled

VIH

VIL

XVPENH

DIN

28F128 Datasheet(PDF) 17 Page - Intel Corporation

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