28F128 datasheet(22/58 Pages) INTEL

22 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

4.2.5

System Interface Information

The following device information can optimize system interface software.

17h

Alternate vendor command set and control interface ID code.

17:

--00

0000h means no second vendor-specified algorithm exists

18:

--00

19h

Secondary algorithm Extended Query Table address.

19:

--00

0000h means none exists

1A:

--00

Table 9.

CFI Identification

Offset

Length

Description

Add.

Hex

Code

Value

Table 10. System Interface Information

Offset

Length

Description

Add.

Hex

Code

Value

1Bh

VCC logic supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1B:

--27

2.7 V

1Ch

VCC logic supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 BCD volts

1C:

--36

3.6 V

1Dh

VPP [programming] supply minimum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

1D:

--00

0.0 V

1Eh

VPP [programming] supply maximum program/erase voltage

bits 0–3 BCD 100 mV

bits 4–7 HEX volts

1E:

--00

0.0 V

1Fh

“n” such that typical single word program time-out = 2n µs

1F:

--07

128 µs

20h

“n” such that typical max. buffer write time-out = 2n µs

20:

--07

128 µs

21h

“n” such that typical block erase time-out = 2n ms

21:

--0A

1 s

22h

“n” such that typical full chip erase time-out = 2n ms

22:

--00

23h

“n” such that maximum word program time-out = 2n times

typical

23:

--04

2 ms

24h

“n” such that maximum buffer write time-out = 2n times typical

24:

--04

2 ms

25h

“n” such that maximum block erase time-out = 2n times typical

25:

--04

16 s

26h

“n” such that maximum chip erase time-out = 2n times typical

26:

--00

28F128 Datasheet(PDF) 22 Page - Intel Corporation

28F128 Datasheet(HTML) 22 Page - Intel Corporation

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