28F128 datasheet(45/58 Pages) INTEL

45 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

5.4

Input Signal Transitions - Reducing Overshoots and

Undershoots When Using Buffers or Transceivers

As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory

devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory

specifications. (See “Absolute Maximum Ratings” on page 40.) Many buffer/transceiver vendors

now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.

Internal output-damping resistors diminish the nominal output drive currents, while still leaving

sufficient drive capability for most applications. These internal output-damping resistors help

reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-

drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When

considering a buffer/transceiver interface design to flash, devices with internal output-damping

resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For

additional information, please refer to the AP-647 5 Volt Intel StrataFlash™ Memory Design

Guide.

5.5

VCC, VPEN, RP# Transitions

Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of

the specified operating ranges, or RP#

≠ V

IH. If RP# transitions to VIL during block erase,

program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of

tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device

will enter reset/power-down mode. The aborted operation may leave data partially corrupted after

programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase

and lock-bit configuration commands must be repeated after normal operation is restored. Device

power-off or RP# = VIL clears the status register.

The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or

CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/

power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN

during VCC transitions.

After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK,

the CUI must be placed in read array mode via the Read Array command if subsequent access to

the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.

5.6

Power-Up/Down Protection

The device is designed to offer protection against accidental block erasure, programming, or lock-

bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at

power-up.

A system designer must guard against spurious writes for VCC voltages above VLKO when VPEN is

active. Since WE# must be low and the device enabled (see Table 2) for a command write, driving

WE# to VIH or disabling the device will inhibit writes. The CUI’s two-step command sequence

architecture provides added protection against data alteration.

Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock and

unlock capability protects the device against inadvertent programming. The device is disabled

while RP# = VIL regardless of its control inputs.

28F128 Datasheet(PDF) 45 Page - Intel Corporation

28F128 Datasheet(HTML) 45 Page - Intel Corporation

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