28F128 datasheet(41/58 Pages) INTEL

41 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

0606_11b

Figure 12. Set Block Lock-Bit Flowchart

Start

Write 60H,

Block Address

Write 01H,

Block Address

Read Status Register

SR.7 =

Full Status

Check if Desired

Set Lock-Bit Complete

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Command

Set Block Lock-Bit

Setup

Comments

Data = 60H

Addr =Block Address

Read Status Register

Data (See Above)

Voltage Range Error

SR.3 =

Command Sequence

Error

SR.4,5 =

Set Lock-Bit Error

SR.4 =

Set Lock-Bit

Successful

Bus

Operation

Standby

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register

command, in cases where multiple lock-bits are set before full status is

checked.

If an error is detected, clear the status register before attempting retry

or other error recovery.

Standby

Check SR.4, 5

Both 1 = Command Sequence

Error

Standby

Check SR.4

1 = Set Lock-Bit Error

Write

Set Block Lock-Bit

Confirm

Data = 01H

Addr = Block Address

Standby

Repeat for subsequent lock-bit operations.

Full status check can be done after each lock-bit set operation or after

a sequence of lock-bit set operations.

Write FFH after the last lock-bit set operation to place device in read

array mode.

Check SR.7

1 = WSM Ready

0 = WSM Busy

Read

Status Register Data

28F128 Datasheet(PDF) 41 Page - Intel Corporation

28F128 Datasheet(HTML) 41 Page - Intel Corporation

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