28F128 datasheet(52/58 Pages) INTEL

52 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

0606_16

NOTE: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at

the first edge of CE0, CE1, or CE2 that disables the device (see Table 2).

For standard word/byte read operations, R15 (tAPA) will equal R2 (tAVQV).

When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to status register

reads, query reads, or device identifier reads.

Figure 17. AC Waveform for Both Page-Mode and Standard Word/Byte Read Operations

R10

High Z

R13

R11

R12

R4 or R16

Valid

Output

ADDRESSES [A

23-A3]

Disabled (V

IH)

Enabled (V

IL)

X [E]

OE# [G]

WE# [W]

DATA [D/Q]

0-DQ15

RP# [P]

BYTE# [F]

High Z

R14

ADDRESSES [A

2-A0]

Valid

Output

R15

Valid

Output

Valid

Address

Valid

Address

Valid

Address

Valid

Output

Valid

Address

28F128 Datasheet(PDF) 52 Page - Intel Corporation

28F128 Datasheet(HTML) 52 Page - Intel Corporation

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