28F128 datasheet(36/58 Pages) INTEL

36 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

0606_07A

Figure 7. Write to Buffer Flowchart

Start

Write Word or Byte

Count, Block Address

Write Buffer Data,

Start Address

X = 0

X = X + 1

Write Next Buffer Data,

Device Address

Abort Write to

Buffer Command?

Check

X = N?

Another Write to

Buffer?

Read Status Register

SR.7 =

Programming

Complete

Read Extended

Status Register

XSR.7 =

Yes

Write to Buffer

Aborted

Yes

Full Status

Check if Desired

Program Buffer to Flash

Confirm D0H

Issue Write to Buffer

Command E8H, Block

Address

Write to Another

Block Address

Write to

Buffer Time-Out?

Set Time-Out

Issue Read

Status Command

Yes

Bus

Operation

Command

Comments

Write

Write to Buffer

Data = E8H

Block Address

Read

XSR. 7 = Valid

Addr = Block Address

Standby

Check XSR. 7

1 = Write Buffer Available

0 = Write Buffer Not Available

Write

(Note 1, 2)

Data = N = Word/Byte Count

N = 0 Corresponds to Count = 1

Addr = Block Address

Write

(Note 3, 4)

Data = Write Buffer Data

Addr = Device Start Address

Write

(Note 5, 6)

Data = Write Buffer Data

Addr = Device Address

Write

Program Buffer

to Flash

Confirm

Data = D0H

Addr = Block Address

Read

(Note 7)

Status Register Data with the

Device Enabled, OE# Low

Updates SR

Addr = Block Address

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

1. Byte or word count values on DQ

0 - DQ7 are loaded into the

count register. Count ranges on this device for byte mode are N

= 00H to 1FH and for word mode are N = 0000H to 000FH.

2. The device now outputs the status register when read (XSR is

no longer available).

3. Write Buffer contents will be programmed at the device start

address or destination flash address.

4. Align the start address on a Write Buffer boundary for

maximum programming performance (i.e., A

4 - A0 of the start

address = 0).

5. The device aborts the Write to Buffer command if the current

address is outside of the original block address.

6. The status register indicates an "improper command

sequence" if the Write to Buffer command is aborted. Follow this

with a Clear Status Register command.

7. Toggling OE# (low to high to low) updates the status register.

This can be done in place of issuing the Read Status Register

command.

Full status check can be done after all erase and write sequences

complete. Write FFH after the last operation to reset the device to

read array mode.

28F128 Datasheet(PDF) 36 Page - Intel Corporation

28F128 Datasheet(HTML) 36 Page - Intel Corporation

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