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28F128 Datasheet(PDF) 53 Page - Intel Corporation |
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28F128 Datasheet(HTML) 53 Page - Intel Corporation |
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53 / 58 page ![]() 28F128J3A, 28F640J3A, 28F320J3A Preliminary 47 6.6 AC Characteristics— Write Operations(1,2) NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics–Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low first) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CEX is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 10 ns. 5. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). Versions Valid for All Speeds Unit # Symbol Parameter Notes Min Max W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX) Going Low 3 1 µs W2 tELWL (tWLEL)CEX (WE#) Low to WE# (CEX) Going Low 4 0 ns W3 tWP Write Pulse Width 4 70 ns W4 tDVWH (tDVEH) Data Setup to WE# (CEX) Going High 5 50 ns W5 tAVWH (tAVEH) Address Setup to WE# (CEX) Going High 5 55 ns W6 tWHEH (tEHWH)CEX (WE#) Hold from WE# (CEX) High 10 ns W7 tWHDX (tEHDX) Data Hold from WE# (CEX) High 0 ns W8 tWHAX (tEHAX) Address Hold from WE# (CEX) High 0 ns W9 tWPH Write Pulse Width High 6 30 ns W11 tVPWH (tVPEH)VPEN Setup to WE# (CEX) Going High 3 0 ns W12 tWHGL (tEHGL) Write Recovery before Read 7 35 ns W13 tWHRL (tEHRL)WE# (CEX) High to STS Going Low 8 500 ns W15 tQVVL VPEN Hold from Valid SRD, STS Going High 3,8,9 0 ns |
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