28F128 datasheet(39/58 Pages) INTEL

39 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

0606_09

Figure 10. Block Erase Flowchart

Start

Read

Status Register

SR.7 =

Erase Flash

Block(s) Complete

Full Status

Check if Desired

Suspend Erase

Issue Single Block Erase

Command 20H, Block

Address

Suspend

Erase Loop

Write Confirm D0H

Block Address

Yes

Bus

Operation

Command

Comments

Write

Erase Block

Data = 20H

Addr = Block Address

Write (Note 1)

Erase

Confirm

Data = D0H

Addr = X

Read

Status register data

With the device enabled,

OE# low updates SR

Addr = X

Standby

Check SR.7

1 = WSM Ready

0 = WSM Busy

1. The Erase Confirm byte must follow Erase Setup.

This device does not support erase queuing. Please see

Application note AP-646 For software erase queuing

compatibility.

Full status check can be done after all erase and write

sequences complete. Write FFH after the last operation to

reset the device to read array mode.

28F128 Datasheet(PDF) 39 Page - Intel Corporation

28F128 Datasheet(HTML) 39 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL