28F128 datasheet(31/58 Pages) INTEL

31 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

4.11.1

Read Configuration

The device will support both asynchronous page mode and standard word/byte reads. No

configuration is required.

Status register and identifier only support standard word/byte single read operations.

Table 18. Read Configuration Register Definition

4.12

Configuration Command

The Status (STS) pin can be configured to different states using the Configuration command. Once

the STS pin has been configured, it remains in that configuration until another configuration

command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation

where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state

machine is ready for a new operation or suspended. Table 19, “Configuration Coding Definitions”

on page 26 displays the possible STS configurations.

To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed

by the desired configuration code. The three alternate configurations are all pulse mode for use as a

system interrupt as described below. For these configurations, bit 0 controls Erase Complete

interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h

configuration code with the Configuration command resets the STS pin to the default RY/BY#

level mode. The possible configurations and their usage are described in Table 19, “Configuration

Coding Definitions” on page 26. The Configuration command may only be given when the device

is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in

both status register bits SR.4 and SR.5 being set to “1.” When configured in one of the pulse

modes, the STS pin pulses low with a typical pulse width of 250 ns.

16 (A16)

121110

Notes

RCR.16 = READ MODE (RM)

0 = Standard Word/Byte Reads Enabled (Default)

1 = Page-Mode Reads Enabled

Read mode configuration effects reads from the flash array.

Status register, query, and identifier reads support standard

word/byte read cycles.

RCR.15–1 = RESERVED FOR FUTURE ENHANCEMENTS (R)

These bits are reserved for future use. Set these bits to “0.”

28F128 Datasheet(PDF) 31 Page - Intel Corporation