28F128 datasheet(33/58 Pages) INTEL

33 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

4.14

Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-

bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while

the WSM is running or the device is suspended.

Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup

is first written. The device automatically outputs status register data when read (see Figure 13 on

page 36). The CPU can detect completion of the clear block lock-bits event by analyzing the STS

pin output or status register bit SR.7.

When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit

error is detected, the status register should be cleared. The CUI will remain in read status register

mode until another command is issued.

This two-step sequence of set-up followed by execution ensures that block lock-bits are not

accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status

only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while

VPEN ≤ VPENLK, SR.3 and SR.5 will be set to “1.”

If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range,

block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required

to initialize block lock-bit contents to known values.

4.15

Protection Register Program Command

The 3 Volt Intel StrataFlash memory includes a 128-bit protection register that can be used to

increase the security of a system design. For example, the number contained in the protection

or ASIC, preventing device substitution.

The 128-bits of the protection register are divided into two 64-bit segments. One of the segments is

programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other

segment is left blank for customer designers to program as desired. Once the customer segment is

programmed, it can be locked to prevent reprogramming.

4.15.1

Reading the Protection Register

The protection register is read in the identification read mode. The device is switched to this mode

by writing the Read Identifier command (90H). Once in this mode, read cycles from addresses

shown in Table 20 or Table 21 retrieve the specified information. To return to read array mode,

write the Read Array command (FFH).

4.15.2

Programming the Protection Register

The protection register bits are programmed using the two-cycle Protection Program command.

The 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for

byte-wide parts. First write the Protection Program Setup command, C0H. The next write to the

28F128 Datasheet(PDF) 33 Page - Intel Corporation