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28F128 Datasheet(PDF) 55 Page - Intel Corporation

Part # 28F128
Description  3 Volt Intel StrataFlash Memory
PDF  58 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

28F128 Datasheet(HTML) 55 Page - Intel Corporation

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28F128J3A, 28F640J3A, 28F320J3A
Preliminary
49
0606_17
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0,
CE1, or CE2 that disables the device (see Table 2).
STS is shown in its default mode (RY/BY#).
a. VCC power-up and standby.
b. Write block erase, write buffer, or program setup.
c. Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.
Figure 18. AC Waveform for Write Operations
A
IN
A
IN
AB
C
D
E
F
W15
D
IN
W11
Valid
SRD
D
IN
D
IN
W13
W7
W3
W4
High Z
W2
W9
W16
W12
W6
W1
W5
W8
V
IH
V
IL
ADDRESSES [A]
Disabled (V
IH)
Enabled (V
IL)
CE
X, (WE#) [E(W)]
V
IH
V
IL
OE# [G]
Disabled (V
IH)
Enabled (V
IL)
WE#, (CE
X) [W(E)]
V
IH
V
IL
DATA [D/Q]
V
OH
V
OL
STS [R]
V
IH
V
IL
RP# [P]
V
PENLK
V
IL
V
PEN [V]
V
PENH



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