28F128 datasheet(37/58 Pages) INTEL

37 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

Figure 8. Byte/Word Program Flowchart

Start

Write 40H,

Address

Write Data and

Address

Read Status

SR.7 =

Full Status

Check if Desired

Byte/Word

Program Complete

Read Status

(See Above)

Voltage Range Error

Device Protect Error

Programming Error

Byte/Word

Program

Successful

SR.3 =

SR.1 =

SR.4 =

FULL STATUS CHECK PROCEDURE

Bus

Operation

Write

Standby

1. Toggling OE# (low to high to low) updates the status register. This

can be done in place of issuing the Read Status Register command.

Repeat for subsequent programming operations.

SR full status check can be done after each program operation, or

after a sequence of programming operations.

Write FFH after the last program operation to place device in read

array mode.

Bus

Operation

Standby

Toggling OE# (low to high to low) updates the status register. This can

be done in place of issuing the Read Status Register command.

Repeat for subsequent programming operations.

SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register

command in cases where multiple locations are programmed before

full status is checked.

If an error is detected, clear the status register before attempting retry

or other error recovery.

Command

Setup Byte/

Word Program

Byte/Word

Program

Comments

Data = 40H

Addr = Location to Be Programmed

Data = Data to Be Programmed

Addr = Location to Be Programmed

Check SR.7

1 = WSM Ready

0 = WSM Busy

Command

Comments

Check SR.3

1 = Programming to Voltage Error

Detect

Check SR.4

1 = Programming Error

Read

(Note 1)

Status Register Data

Standby

Check SR.1

1 = Device Protect Detect

RP# = V

IH, Block Lock-Bit Is Set

Only required for systems

implemeting lock-bit configuration.

28F128 Datasheet(PDF) 37 Page - Intel Corporation

28F128 Datasheet(HTML) 37 Page - Intel Corporation

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