28F128 datasheet(28/58 Pages) INTEL

28 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

4.5

Clear Status Register Command

Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by

the Clear Status Register command. These bits indicate various failure conditions (see Table 16).

By allowing system software to reset these bits, several operations (such as cumulatively erasing or

locking multiple blocks or writing several bytes in sequence) may be performed. The status register

may be polled to determine if an error occurred during the sequence.

To clear the status register, the Clear Status Register command (50H) is written. It functions

independently of the applied VPEN voltage. The Clear Status Register command is only valid when

the WSM is off or the device is suspended.

4.6

Block Erase Command

Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is

first written, followed by an block erase confirm. This command sequence requires an appropriate

address within the block to be erased (erase changes all block data to FFH). Block preconditioning,

erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle

block erase sequence is written, the device automatically outputs status register data when read (see

Figure 10, “Block Erase Flowchart” on page 33). The CPU can detect block erase completion by

analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE0, CE1, or CE2 to

update the status register.

When the block erase is complete, status register bit SR.5 should be checked. If a block erase error

is detected, the status register should be cleared before system software attempts corrective actions.

The CUI remains in read status register mode until a new command is issued.

This two-step command sequence of set-up followed by execution ensures that block contents are

not accidentally erased. An invalid Block Erase command sequence will result in both status

is valid and VPEN = VPENH. If block erase is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will

be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared. If

block erase is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set to

“1.”

4.7

Block Erase Suspend Command

The Block Erase Suspend command allows block-erase interruption to read or program data in

another block of memory. Once the block erase process starts, writing the Block Erase Suspend

command requests that the WSM suspend the block erase sequence at a predetermined point in the

algorithm. The device outputs status register data when read after the Block Erase Suspend

command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase

operation has been suspended (both will be set to “1”). In default mode, STS will also transition to

VOH. Specification tWHRH defines the block erase suspend latency.

At this point, a Read Array command can be written to read data from blocks other than that which

is suspended. A program command sequence can also be issued during erase suspend to program

data in other blocks. During a program operation with block erase suspended, status register bit

SR.7 will return to “0” and STS output (in default mode) will transition to VOL. However, SR.6

will remain “1” to indicate block erase suspend status. Using the Program Suspend command, a

program operation can also be suspended. Resuming a suspended programming operation by

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