28F128 datasheet(26/58 Pages) INTEL

26 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

NOTES:

1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is

A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h).

2. X selects the specific block’s lock configuration code. See Figure 5 for the device identifier code memory

map.

4.4

Read Status Register Command

The status register may be read to determine when a block erase, program, or lock-bit configuration

is complete and whether the operation completed successfully. It may be read at any time by

writing the Read Status Register command. After writing this command, all subsequent read

operations output data from the status register until another valid command is written. Page-mode

reads are not supported in this read mode. The status register contents are latched on the falling

edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 2, “Chip

Enable Truth Table” on page 7). OE# must toggle to VIH or the device must be disabled (see Table

2) before further reads to update the status register latch. The Read Status Register command

functions independently of the VPEN voltage.

During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid

until the Write State Machine completes or suspends the operation. Device I/O pins DQ0–DQ6 and

DQ8–DQ15 are placed in a high-impedance state. When the operation completes or suspends

(check status register bit 7), all contents of the status register are valid when read.

Table 15. Identifier Codes

Code

Address(1)

Data

Manufacture Code

00000

(00) 89

Device Code

32-Mbit

00001

(00) 16

64-Mbit

00001

(00) 17

128-Mbit

00001

(00) 18

Block Lock Configuration

0002(2)

• Block Is Unlocked

DQ0 = 0

• Block Is Locked

DQ0 = 1

• Reserved for Future Use

DQ1–7

28F128 Datasheet(PDF) 26 Page - Intel Corporation

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